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NXP Semiconductors /MIMXRT1052 /USBPHY1 /PWD_CLR

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Interpret as PWD_CLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RSVD00 (TXPWDFS)TXPWDFS 0 (TXPWDIBIAS)TXPWDIBIAS 0 (TXPWDV2I)TXPWDV2I 0RSVD10 (RXPWDENV)RXPWDENV 0 (RXPWD1PT1)RXPWD1PT1 0 (RXPWDDIFF)RXPWDDIFF 0 (RXPWDRX)RXPWDRX 0RSVD2

Description

USB PHY Power-Down Register

Fields

RSVD0

Reserved.
TXPWDFS

0 = Normal operation
TXPWDIBIAS

0 = Normal operation
TXPWDV2I

0 = Normal operation
RSVD1

Reserved.
RXPWDENV

0 = Normal operation
RXPWD1PT1

0 = Normal operation
RXPWDDIFF

0 = Normal operation
RXPWDRX

0 = Normal operation
RSVD2

Reserved.

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data